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dpl 4519g sound processor for digital and analog edition oct. 31, 2000 6251-512-1pd preliminar y d a t a sheet micr onas micronas surround systems
dpl 4519g preliminary data sheet 2 micronas contents page section title 4 1. introduction 5 1.1. features of the dpl 4519g 6 1.2. application fields of the dpl 4519g 7 2. functional description 7 2.1. architecture of the dpl 4519g family 8 2.2. preprocessing i 2 s input signals 8 2.3. selection of internal processed surround signals 8 2.4. source selection and output channel matrix 8 2.5. audio baseband processing 8 2.5.1. main and aux outputs 8 2.6. surround processing 8 2.6.1. surround processing mode 8 2.6.1.1. decoder matrix 9 2.6.1.2. surround reproduction 9 2.6.1.3. center modes 9 2.6.1.4. useful combinations of surround processing modes 10 2.6.2. examples 11 2.6.3. application tips for using 3d-panorama 11 2.6.3.1. sweet spot 11 2.6.3.2. clipping 11 2.6.3.3. loudspeaker requirements 11 2.6.3.4. cabinet requirements 11 2.6.4. input and output levels for dolby surround pro logic 11 2.7. scart signal routing 11 2.7.1. scart out select 12 2.7.2. stand-by mode 12 2.8. i 2 s bus interfaces 12 2.8.1. synchronous i 2 s-interface(s) 12 2.8.2. asynchronous i 2 s-interface 12 2.8.3. multichannel i 2 s-output 12 2.8.4. asynchronous multichannel i 2 s-input 13 2.9. digital control i/o pins 13 2.10. clock pll oscillator and crystal specifications 14 3. control interface 14 3.1. i 2 c bus interface 14 3.1.1. device and subaddresses 14 3.1.2. internal hardware error handling 15 3.1.3. description of control register 15 3.1.4. protocol description 16 3.1.5. proposals for general dpl 4519g i 2 c telegrams 16 3.1.5.1. symbols 16 3.1.5.2. write telegrams 16 3.1.5.3. read telegrams 16 3.1.5.4. examples 16 3.2. start-up sequence: power-up and i 2 c controlling
contents, continued page section title preliminary data sheet dpl 4519g micronas 3 16 3.3. dpl 4519g programming interface 16 3.3.1. user registers overview 19 3.3.2. description of user registers 19 3.3.2.1. write registers on i 2 c subaddress 10 hex 21 3.3.2.2. read registers on i 2 c subaddress 11 hex 21 3.3.2.3. write registers on i 2 c subaddress 12 hex 33 3.3.2.4. read registers on i 2 c subaddress 13 hex 34 3.4. programming tips 34 3.5. examples of minimum initialization codes 34 3.5.1. micronas dolby digital chipset (with mas 3528e) 35 4. specifications 35 4.1. outline dimensions 37 4.2. pin connections and short descriptions 40 4.3. pin descriptions 43 4.4. pin configurations 45 4.5. pin circuits 47 4.6. electrical characteristics 47 4.6.1. absolute maximum ratings 48 4.6.2. recommended operating conditions (t a = 0 to 70 c) 48 4.6.2.1. general recommended operating conditions 48 4.6.2.2. analog input and output recommendations 49 4.6.2.3. crystal recommendations 50 4.6.3. characteristics 50 4.6.3.1. general characteristics 51 4.6.3.2. digital inputs, digital outputs 52 4.6.3.3. reset input and power-up 53 4.6.3.4. i 2 c-bus characteristics 54 4.6.3.5. i 2 s-bus characteristics 56 4.6.3.6. analog baseband inputs and outputs, agndc 58 4.6.3.7. power supply rejection 58 4.6.3.8. analog performance 61 5. appendix a: application information 61 5.1. phase relationship of analog outputs 62 5.2. application circuit 64 6. data sheet history license notice: dolby pro logic and dolby digital are trademarks of dolby laboratories. supply of this implementation of dolby technology does not convey a license nor imply a right under any patent, or any other in dustrial or intellec- tual property right of dolby laboratories, to use this implementation in any finished end-user or ready-to-use final product. c ompanies planning to use this implementation in products must obtain a license from dolby laboratories licensing corporation before designing such p roducts.
dpl 4519g preliminary data sheet 4 micronas sound processor for digital and analog surround systems the hardware and software description in this docu- ment is valid for the dpl 4519g version a1 and follow- ing versions. 1. introduction the dpl 4519g processor is designed as part of the micronas chip set for digital and analog surround sys- tems i. e. dolby digital, mpeg 2 audio, or dolby pro- logic. the combination of mas 3528e, dpl 4519g, and msp 44x0g is a complete 5.1 channel dolby digi- tal decoder and playback solution, while dpl 4519g and msp 44x0g alone, represent a complete dolby surround pro logic system. the dpl 4519g receives its incoming data via highly flexible i 2 s interfaces. the three i 2 s input interfaces can be configured as three asynchronous i 2 s inputs or two synchronous and one asynchronous interface. in the latter case, the asynchronous interface allows reception of 2-8 channels with arbitrary sample rate ranging from 8 to 48 khz. the synchronization is per- formed by means of an adaptive high-quality sample rate converter. in an application together with the dolby digital decoder mas 3528e, eight channels (left, right, sur- round left, surround right, center, subwoofer, pro logic encoded left, pro logic encoded right) are fed in and processed in the dpl 4519g. similar to the multichannel i 2 s input interface, the dpl is provided with an 8-channel i 2 s output interface, which can be connected to a msp 44x0g. therefore all 8 channels can be routed to each output in both ics. the baseband processing including e.g. balance, bass, treble, and loudness is performed at a fixed sam- ple rate of 48 khz. fig. 1C1 shows a simplified functional block diagram of the dpl 4519g. the dpl 4519g is pin-compatible to members of the msp 34xx family. this speeds up pcb development for customers using msps. the software interface of the dpl 4519g is also largely the same as for members of the msp family. the ics are produced in submicron cmos technology and are available in pqfp80, plqfp64 and in psdip64 packages. fig. 1C1: simplified block diagram of the dpl 4519g source select main scart1 scart2 aux i 2 s dac dac main dac scart output select i 2 s2 i 2 s1 i 2 s i 2 s i 2 s3 sound processing aux sound processing (2..8-channel) (8-channel) i 2 s prescale prologic processing scart1 scart2 scart4 scart3 mono subwoofer
preliminary data sheet dpl 4519g micronas 5 1.1. features of the dpl 4519g C 8-channel asynchonous i 2 s input interface (multichannel mode) + 2 synchronous i 2 s input channels (e.g. for msp and adr) or 3 asynchronous two-channel i 2 s input interfaces C main and aux channel with balance, bass, treble, loudness, volume C 5-band graphic equalizer for main channel C dolby surround pro logic adaptive matrix C micronas effect matrix C micronas 3d-panorama virtualizer compliant to virtual dolby surround technology C micronas panorama sound mode (3d surround sound via two loudspeakers) C noise generator C spatial effect for surround C 30-ms surround delay C surround matrix control: adaptive/passive/effect C center mode control: normal/phantom/wide/off C surround reproduction control: rear speaker, front speaker, panorama, 3d-panorama C two digital input/output pins controlled by i 2 c bus fig. 1C2 shows a typical dolby digital application using dpl 4519g, msp 4450g, and mas 3528e.
dpl 4519g preliminary data sheet 6 micronas 1.2. application fields of the dpl 4519g fig. 1C2: typical dpl 4519g application dpl 4519g pro logic decoder i2s_ws3 i2s_cl3 6 channel loop-through or dolby pro logic decoder i2s_1_l i2s_1_r i2s_3_r t i2s_3_l t audio_ cl_out sif-in i2s_ws i2s_cl main aux i2s_ws i2s_cl demod scart1_in scart4_in a/d 2 . . . i2s_2_l i2s_2_r r l s l sub bass treble balance volume bass treble balance volume msp 4450g multistandard sound processor i2s_1_l i2s_1_r i2s_2_l i2s_2_r sound- process. balance volume bass treble balance volume volume volume 18.432 mhz i2s_inputs 123 123 i2s_inputs d/a analog volume d/a d/a i2s_ws3 i2s_cl3 configuration examples 2-8 channel serial input i2s_3_l t i2s_3_s l main aux scart1 scart2 normal d/a analog volume d/a analog volume d/a analog volume c int c int l t r t l t r t l, r l ext sub ext dolby digital / pro logic s l s r c int sub ext l, r c, sub sl, sr l t , r t l int r int subw int l t r t l t r t l, r --- --- --- --- --- l r subw l r l r l, r subw int 12 basic tv- sound system dolby digital upgrade module l, r c, sub sl, sr l t , r t 18.432 mhz dolby digital: (l t , r t , l, r, s l , s r , c, sub) pro logic: (l t , r t , l, r, c, subw) i2s_out_l/r i2s_out_l/r s l s r i2s_3_r i2s_3_sub s/pdif out pcm-format (lt/rt or l/r or lo/ro) or loop-through (e.g. dts) 18.432 mhz i2s-mode:multichannel mode auf d0 (6 - 8 channels, fs=32, 44.1 or 48 khz, 16,18,....32 bit) i2s-in: slave l t r t --- --- l t r t 2 volume d/a scart1 i2s_3_r t r ext (c int ) --- l t r t l t r t l r i2s_3_l i2s_3_s r i2s_3_c 2-8 ch. input (l t , r t ,l, r s l , s r ,c, sub) s r c dolby digital / pro logic configurations example 1: - internal l, c, r - internal woofer for low freq. of l, (c), r - ext. surround speakers s l , s r - ext. subwoofer for sub channel. example 2: - internal left and right used as c - internal woofer for low freq. of c - ext. l, r - ext. surround speakers s l , s r - ext. subwoofer for sub channel. mas 3528e dolby digital decoder mpeg-l2 decoder sic sii sid sic* sii* sid* soc soi sod sod1 sod2 sod3 input buffer deemphasis post processing delay lines ac-3 pcm mpeg l r lt rt ls rs amp./ osc. pll synth. clko noise gen. multipl. c/ sub s/pdi1 spdo s/pdif in 1/2 ac-3, mpeg l2, pcm or other format s/pdi2
preliminary data sheet dpl 4519g micronas 7 2. functional description 2.1. architecture of the dpl 4519g family fig. 2C1 shows a simplified block diagram of the ic. volume prescale daca_l daca_r i 2 s channel matrix main channel matrix aux channel matrix volume i2s interface i 2 s interface i 2 s interface sc1_in_l sc1_in_r sc2_in_l sc2_in_r sc3_in_l sc3_in_r sc4_in_l sc4_in_r mono_in prescale i2s_da_out i2s_da_in1 i2s_da_in3 d a synchronization (sync. 48khz) (async. 8-48 khz) dacm_l dacm_r volume i 2 s1 i 2 s3 sc1_out_l sc1_out_r sc2_out_l sc2_out_r scart output select i 2 s interface prescale i2s_da_in2 i 2 s2 (sync. 48khz) (sync. 48khz) i2s_cl i2s_ws i2s_cl3 i2s_ws3 (16 hex ) (12 hex ) (11 hex ) (08 hex ) (09 hex ) (0b hex ) (06 hex ) (00 hex ) beeper s s (14 hex ) fig. 2 C1: signal flow block diagram of the dpl 4519g (input and output names correspond to pin names) source select 8 9 10 6 5 7 l t r t l r s l s r c sub i2s_3 resorting matrix (36 hex ) d a scart1 channel matrix (0a hex ) (07 hex ) scart1_l/r surround channel matrix (48 hex ) noise generator surround processing balance bass/ tre bl e / loudness/ equalizer balanc subwoo- fer level adjust dacm_sub d a bass/ tre bl e / loudness internal/external switch (36 hex ) (49 hex ) (4a hex ) (4b hex ) (4c hex ) (4d hex ) (2c hex ) (31/32/33 hex ) (02/03/04 hex ) (01 hex ) (20..25 hex ) (30 hex ) l r s l s r c sub
dpl 4519g preliminary data sheet 8 micronas 2.2. preprocessing i 2 s input signals the i 2 s inputs can be adjusted in level by means of the i 2 s prescale registers. the i 2 s_3 interface is able to receive more than two channels (see section 2.6. on page 8). the incoming signals can be resorted by a programmable matrix in order to obtain a certain order, which means an unified postprocessing afterwards. since the i 2 s_3 interface is asynchronous, incoming sound signals with arbitrary sample rates in the range of 8-48 khz are interpolated to 48 khz by means of an adaptive high quality sample rate converter. therefore all subsequent processing is calculated on a fixed sampling rate, which even can be synchronized to i2s_ws e.g. to a msp 4450 being locked to an incom- ing nicam signal. 2.3. selection of internal processed surround signals instead of having an multichannel input via the i 2 s_3 interface, a multichannel signal can be created by an internal dolby pro logic decoder. in that case chan- nels 3..8 of the multichannel input are replaced by the internally generated signals. 2.4. source selection and output channel matrix the source selector makes it possible to distribute all source signals (i 2 s input signals) to the desired output channels (main, aux, etc.). all input and output signals can be processed simultaneously. each source chan- nel is identified by a unique source address. for each output channel, the output channel matrix can be set to sound a (left mono), sound b (right mono), stereo, or mono (sound left and right). 2.5. audio baseband processing 2.5.1. main and aux outputs the following baseband features are implemented in the main and aux output channels: bass/treble, loud- ness, balance, and volume. a square wave beeper can be added to these outputs. the main channel addition- ally supports an equalizer function (this is not simulta- neously available with bass/treble). 2.6. surround processing 2.6.1. surround processing mode surround sound processing is controlled by three func- tions: the "decoder matrix" defines which method is used to create a multichannel signal (l, c, r, s) out of a stereo input. the "surround reproduction" determines whether the surround signal s is fed to surround speakers. if no surround speaker is actually connected, it defines the method that is used to create surround effects. the center mode determines how the center signal c is to be processed. it can be left unmodified, dis- tributed to left and right, discarded or high pass fil- tered, whereby the low pass signals are distributed to left and right. 2.6.1.1. decoder matrix the decoder matrix allows three settings: C adaptive: the adaptive matrix is used for dolby surround pro logic. even sound material not encoded in dolby surround will produce good surround effects in this mode. the use of the adaptive matrix requires a license from dolby laboratories (see license notice on page 3). C pa s siv e: a simple fixed matrix is used for surround sound. C effect: a fixed matrix that is used for mono sound and spe- cial effects. with adaptive or passive matrix no sur- round signal is present in case of mono, moreover in adaptive mode even the left and right output chan- nels carry no signal (or just low frequency signals in case of center mode = normal). if surround sound is still required for mono signals, the effect matrix can be used. this forces the surround chan- nel to be active. the effect matrix can be used together with 3d-panorama. the result will be a pseudo stereo effect or a broadened stereo image respectively.
preliminary data sheet dpl 4519g micronas 9 2.6.1.2. surround reproduction surround sound can be reproduced with four choices: C rear_speaker: if there are any surround speakers connected to the system, this mode should be used. useful loud- speaker combinations are (l, c, r, s) or (l, r, s). C front_speaker: if there is no surround speaker connected, this mode can be used. surround information is mixed to left and right output but without creating the illusion of a virtual speaker. it is similar to stereo but an additional center speaker can be used. this mode should be used with the adaptive decoder matrix only. useful loudspeaker combinations are (l, c, r) (note: the surround output channel is muted). C panorama: the surround information is mixed to left and right in order to create the illusion of a virtual surround speaker. useful loudspeaker combinations are (l, c, r) or (l, r) (note: the surround output channel is muted). C 3d-panorama: like panorama with improved effect. this algo- rithm has been approved by the dolby laboratories for compliance with the "virtual dolby surround" technology. useful loudspeaker combinations are (l, c, r) or (l, r) (note: the surround output chan- nel is muted). 2.6.1.3. center modes four center modes are supported: C normal: small center speaker connected, l and r speakers have better bass capability. center signal is high pass filtered. C wide: l, r, and c speakers all have good bass capability. C phantom: no center speaker used. center signal is distributed to l and r (note: the center output channel c is muted). C off: no center speaker used. center signal c is dis- carded (note: the center output channel c is muted). 2.6.1.4. useful combinations of surround processing modes in principle, "decoder matrix", "surround reproduc- tion", and "center modes" are independent settings (all "decoder matrix" settings can be used with all "sur- round reproduction" and "center modes") but there are some combinations that do not create "good" sound. useful combinations are surround reproduction and center modes C rear_speaker: this mode is used if surround speakers are avail- able. useful center modes are normal, wide, phantom, and off. C front_speaker: this mode can be used if no surround speaker but a center speaker is connected. useful center modes are normal and wide. C panorama or 3d-panorama: no surround speaker used. two (l and r) or three (l, r, and c) loudspeakers can be used. useful center modes are normal, wide, phantom, and off. center modes and decoder matrix C phantom: should only be used together with adaptive decoder matrix. C normal and wide: can be used together with any surround decoder matrix. C off: this mode can be used together with the passive and effect decoder matrix (no center speaker connected).
dpl 4519g preliminary data sheet 10 micronas 2.6.2. examples table 2C1 shows some examples of how these modes can be used to configure the ic. the list is not intended to be complete, more modes are possible. table 2C1: examples of surround configurations configurations speaker config- uration 1) surround processing mode register (4b hex ) decoder matrix [15:8] surround reproduction [7:4] center mode [3:0] stereo stereo (l,r) -- - surround modes as defined by dolby laboratories 2) dolby surround pro logic (l,c,r,s) adaptive rear_ speaker normal wide (l,r,s) adaptive rear_ speaker phantom dolby 3 stereo (l,c,r) adaptive front_ speaker normal wide virtual dolby surround (l,r) adaptive 3d_panorama phantom surround modes that use the dolby adaptive matrix 2) 3-channel virtual surround (l,c,r) adaptive 3d_panorama normal wide passive matrix surround sound 4-channel surround (l,c,r,s) passive rear_ speaker normal wide 3-channel surround (l,r,s) passive rear_ speaker off 2-channel micronas 3d surround sound (mss) (l,r) passive 3d_panorama off 3-channel micronas 3d surround sound (mss) (l,c,r) passive 3d_panorama normal wide special effects surround sound 4-channel surround for mono (l,c,r,s) effect rear_ speaker normal wide 2-channel virtual surround for mono (l,r) effect 3d_panorama off 3-channel virtual surround for mono (l,c,r) effect 3d_panorama normal wide 1) speakers not in use are muted automatically. 2) the implementation in products requires a license from dolby laboratories licensing corporation (see note on page 3).
preliminary data sheet dpl 4519g micronas 11 2.6.3. application tips for using 3d-panorama 2.6.3.1. sweet spot good results are only obtained in a rather close area along the middle axis between the two loudspeakers: the sweet spot. moving away from this position degrades the effect. 2.6.3.2. clipping for the test at dolby labs, it is very important to have no clipping effects even with worst case signals. the i 2 s-prescale register has to be set to values of max 10 hex (16 dec ). this is sufficient in terms of clipping. however, it was found, that by reducing the prescale to a value lower than 16 dec more convincing effects are generated in case of very high dynamic signals. a value of 10 dec is a good compromise between overall volume and additional headroom. test signals: sine sweep with 0 dbfs; l only, r only, l&r equal phase, l&r anti phase. listening tests: dolby trailers (train trailer, city trailer, canyon trailer...) 2.6.3.3. loudspeaker requirements the loudspeakers used and their positioning inside the tv set will greatly influence the performance of the vir- tualizer. the algorithm works with the direct sound path. reflected sound waves reduce the effect. so its most important to have as much direct sound as possi- ble, compared to indirect sound. to obtain the approval for a tv set, dolby laboratories require mounting the loudspeakers at the front of the set. loudspeakers radiating to the side of the tv set will not produce convincing effects. good directionality of the loudspeakers towards the listener is optimal. the virtualizer was specially developed for implemen- tation in tv sets. even for rather small stereo tv's, suf- ficient sound effects can be obtained. for small sets, the loudspeaker placement should be to the side of the crt; for large screen sets (or 16:9 sets), mounting the loudspeakers below the crt is acceptable (large sep- aration is preferred, low frequency speakers should be outmost to avoid cancellation effects). using external loudspeakers with a large stereo base will not create optimal effects. the loudspeakers should be able to reproduce a wide frequency range. the most important frequency range starts from 160 hz and ranges up to 5 khz. great care has to be taken with systems that use one common subwoofer: a single loudspeaker cannot reproduce virtual sound locations. the crossover fre- quency must be lower than 120 hz. 2.6.3.4. cabinet requirements during listening tests at dolby laboratories, no reso- nances in the cabinet should occur. good material to check for resonances are the dolby trailers or other dynamic sound tracks. 2.6.4. input and output levels for dolby surround pro logic the nominal input level (input sensitivity) for the i 2 s- inputs is - 15 dbfs. the highest possible input level of 0 dbfs is accepted without internal overflow. the i 2 s- prescale value should be set to values of max 0 db (16 dec ). with higher prescale values lower input sensitivities can be accommodated. a higher input sensitivity is not possible, because at least 15 db headroom is required for every input according to the dolby specifications. a full-scale left only input (0 dbfs) will produce a full- scale left only output (at 0 db volume). the typical out- put level is 1.37 vrms for dacm_l. the same holds true for right only signals (1.37 vrms for dacm_r). a full-scale input level on both inputs (lin=rin=0 dbfs) will give a center only output with maximum level. a full-scale input level on both inputs (but lin and rin with inverted phases) will give a surround-only signal with maximum level. for reproducing dolby pro logic according to its spec- ifications, the center and surround outputs must be amplified by 3 db with respect to the l and r output signals. this can be done in two ways: 1. by implementing 3 db more amplification for center and surround loudspeaker outputs. 2. by always selecting volume for l and r 3 db lower than center and surround. method 1 is preferable, as method 2 lowers the achievable snr for left and right signals by 3 db. 2.7. scart signal routing 2.7.1. scart out select the scart output select block includes full matrix switching facilities. the switches are controlled by the acb user register (see page page 30).
dpl 4519g preliminary data sheet 12 micronas 2.7.2. stand-by mode if the dpl 4519g is switched off by first pulling standbyq low and then (after >1 m s delay) switching off dvsup and avsup, but keeping ahvsup ( stand- by-mode ), the scart switches maintain their posi- tion and function. this allows the copying from selected scart-inputs to scart-outputs in the tv sets stand-by mode. in case of power on or starting from stand-by (see details on the power-up sequence in fig. 4C19 on page 52), all internal registers except the acb register (page 30) are reset to the default configuration (see table 3C5 on page 17). the reset position of the acb register becomes active after the first i 2 c transmission into the baseband processing part (subaddress 12 hex ). by transmitting the acb register first, the reset state can be redefined. 2.8. i 2 s bus interfaces the dpl 4519g has two kinds of interfaces: synchron master/slave input/output interfaces running on 48 khz and an asynchron slave interface. the interfaces accept a variety of formats with different sample width, bit-orientation, and wordstrobe timing. all i 2 s options are set by means of the modus or i 2 s_config register. 2.8.1. synchronous i 2 s-interface(s) the synchronous i 2 s bus interface consists of the pins: C i2s_da_in1, i2s_da_in2/3 (i2s_da_in2 in pqfp80 package): i 2 s serial data input, 16, 18...32 bits per sample. Ci2s_da_out: i 2 s serial data output, 16, 18...32 bits per sample. C i2s_cl: i 2 s serial clock. Ci2s_ws: i 2 s word strobe signal defines the left and right sample. if the dpl 4519g serves as the master on the i 2 s interface, the clock and word strobe lines are driven by the dpl 4519g. in this mode, only 16, 32 bits per sample can be selected. in slave mode, these lines are input to the dpl 4519g and the dpl 4519g clock is synchronized to 384 times the i2s_ws rate (48 khz). an i 2 s timing diagram is shown in fig. 4C21 on page 55. 2.8.2. asynchronous i 2 s-interface the asynchronous i 2 s slave interface allows the reception of digital audio signals with arbitrary sample rates from 5 to 50 khz. the synchronization is per- formed by means of an adaptive sample rate con- verter. no oversampling clock is required. the following pins are used for the asynchronous i 2 s bus interface (serve only as input): C i2s_ws3 C i2s_cl3 C i2s_da_in2/3 (i2s_da_in3 in pqfp80 package). the interface accepts i 2 s-input streams with msb first and with sample widths of 16,18...32 bits. with left/ right alignment and wordstrobe timing polarity, there are additional parameters available for the adaption to a variety of formats in the i2s configuration reg- ister. 2.8.3. multichannel i 2 s-output bit[0:1] of the i2s configuration register (see page 20) switches the output to 8 channel multichan- nel output mode. the bit resolution per channel is 32 bit in master mode. while the first two channels can be selected on the source select matrix, channels 3-8 are always connected to the i2s_3 input channels 3-8. both, master and slave mode is possible, as long as as the wordstrobe has only one positive edge per frame in slave mode. 2.8.4. asynchronous multichannel i 2 s-input the dpl 4519g supports two kinds of asynchronous multichannel input: C the asynchronous i2s_3 interface can be switched to multichannel mode (bit [8] of the i2s configu- ration register is set to 1. the number of chan- nels must be even and less or equal eight. C all i2s input lines (i2s_da_in1, i2s_da_in2 and i2s_da_in3 in pqfp80 package) can be switched to asynchronous two channel mode (bit[2] set to 1 in the i2s configuration register). the common clock is i2s_ws3 and i2s_cl3. no synchronous i2s interfaces are available in this mode.
preliminary data sheet dpl 4519g micronas 13 2.9. digital control i/o pins the static level of the digital input/output pins d_ctr_i/o_0/1 is switchable between high and low via the i 2 c-bus by means of the acb register (see page 30). this enables the controlling of external hardware switches or other devices via i 2 c-bus. the modus register can set the digital input/output pins to high impedance (see page 19). so the pins can be used as input. the current state can be read out of the status register (see page page 21). 2.10. clock pll oscillator and crystal specifications the dpl 4519g derives all internal system clocks from the 18.432 mhz oscillator. in i 2 s-slave mode of the synchronous interface, the clock is phase-locked to the corresponding source. for proper performance, the dpl clock oscillator requires a 18.432-mhz crystal. note that for the phase-locked modes (i 2 s-slave), crystals with tighter tolerance are required. the asynchronous i 2 s3 slave interface uses a different locking mechanism and does not require tighter crystal tolerances.
dpl 4519g preliminary data sheet 14 micronas 3. control interface 3.1. i 2 c bus interface 3.1.1. device and subaddresses the dpl 4519g is controlled via the i 2 c bus slave interface. the ic is selected by transmitting one of the dpl 4519g device addresses. in order to allow up to three dpl or msp ics to be connected to a single bus, an address select pin (adr_sel) has been imple- mented. with adr_sel pulled to high, low, or left open, the dpl 4519g responds to different device addresses. a device address pair is defined as a write address and a read address (see table 3C1). writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. reading is done by sending the write device address, followed by the subaddress byte and two address bytes. without sending a stop condi- tion, reading of the addressed data is completed by sending the device read address and reading two bytes of data. refer to section 3.1.4. for the i 2 c bus protocol and to section 3.4. programming tips on page 34 for proposals of dpl 4519g i 2 c telegrams. see table 3C2 for a list of available subaddresses. besides the possibility of hardware reset, the dpl can also be reset by means of the reset bit in the con- trol register by the controller via i 2 c bus. due to the internal architecture of the dpl 4519g, the ic cannot react immediately to an i 2 c request. the typical response time is about 0.3 ms. if the dpl can- not accept another complete byte of data until it has performed some other function (for example, servicing an internal interrupt), it will hold the clock line i2c_cl low to force the transmitter into a wait state. the positions within a transmission where this may happen are indicated by wait in section 3.1.4. the maximum wait period of the dpl during normal operation mode is less than 1 ms. 3.1.2. internal hardware error handling in case of any internal hardware error (e.g. interruption of the power supply of the dpl), the dpls wait period is extended to 1.8 ms. after this time period elapses, the dpl releases data and clock lines. indicating and solving the error status: to indicate the error status, the remaining acknowl- edge bits of the actual i 2 c-protocol will be left high. additionally, bit[14] of control is set to one. the dpl can then be reset via the i 2 c bus by transmitting the reset condition to control. indication of reset: any reset, even caused by an unstable reset line etc., is indicated in bit[15] of control. a general timing diagram of the i 2 c bus is shown in fig. 4C21 on page 55. table 3C1: i 2 c bus device addresses adr_sel low (connected to dvss) high (connected to dvsup) left open mode write read write read write read dpl device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex table 3C2: i 2 c bus subaddresses name binary value hex value mode function control 0000 0000 00 read/write write: software reset of dpl (see table 3C3) read: hardware error status of dpl wr_dem 0001 0000 10 write write address demodulator rd_dem 0001 0001 11 write read address demodulator wr_dsp 0001 0010 12 write write address dsp rd_dsp 0001 0011 13 write read address dsp
preliminary data sheet dpl 4519g micronas 15 3.1.3. description of control register 3.1.4. protocol description write to dsp read from dsp write to control read from control note: s = i 2 c-bus start condition from master p = i 2 c-bus stop condition from master ack = acknowledge-bit: low on i2c_da from slave (= dpl, light gray) or master (= controller dark gray) nak = not acknowledge-bit: high on i2c_da from master (dark gray) to indicate end of read or from dpl indicating internal error state wait = i 2 c-clock line is held low, while the dpl is processing the i 2 c command. this waiting time is max. 1 ms table 3C3: control as a write register name subaddress bit[15] (msb) bits[14:0] control 00 hex 1 : reset 0 : normal 0 table 3C4: control as a read register (only dpl 4519g -versions from a2 on) name subaddress bit[15] (msb) bit[14] bits[13:0] control 00 hex reset status after last reading of control: 0 : no reset occured 1 : reset occured internal hardware status: 0 : no error occured 1 : internal error occured not of interest reading of control will reset the bits[15,14] of control. after power-on, bit[15] of control will be set; it must be read once to be resetted. swrite device address wait ack sub-addr ack addr-byte high ack addr-byte low ack data-byte- high ack data-byte low ack p swrite device address wait ack sub-addr ack addr-byte high ack addr-byte low ack s read device address wait ack data-byte- high ack data-byte low nak p swrite device address wait ack sub-addr ack data-byte high ack data-byte low ack p swrite device address wait ack 00hex ack s read device address wait ack data-byte- high ack data-byte low nak p
dpl 4519g preliminary data sheet 16 micronas fig. 3C1: i 2 c bus protocol (msb first; data must be stable while clock is high) 3.1.5. proposals for general dpl 4519g i 2 c telegrams 3.1.5.1. symbols daw write device address (80 hex , 84 hex or 88 hex ) dar read device address (81 hex , 85 hex or 89 hex ) < start condition > stop condition aa address byte dd data byte 3.1.5.2. write telegrams write to control register write data into demodulator write data into dsp 3.1.5.3. read telegrams read data from control register read data from demodulator read data from dsp 3.1.5.4. examples <80 00 80 00> reset dpl statically <80 00 00 00> clear reset <80 12 00 08 08 20> set main channel source to i2s3 - l/r <80 12 00 00 73 00> set main volume to 0 db more examples of typical application protocols are listed in section 3.4. programming tips on page 34. 3.2. start-up sequence: power-up and i 2 c controlling after power on or reset (see fig. 4C21), the ic is in an inactive state. all registers are in the reset posi- tion, the analog outputs are muted. the controller has to initialize all registers for which a non-default setting is necessary. 3.3. dpl 4519g programming interface 3.3.1. user registers overview the dpl 4519g is controlled by means of user regis- ters. the complete list of all user registers is given in the following tables. the registers are partitioned into two sections: 1. subaddress 10 hex for writing, 11 hex for reading and 2. subaddress 12 hex for writing, 13 hex for reading. write and read registers are 16-bit wide, whereby the msb is denoted bit[15]. transmissions via i 2 c bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). all write registers, except modus and i2s configuration, are readable. unused parts of the 16-bit write registers must be zero. addresses not given in this table must not be accessed. 1 0 s p i2c_da i2c_cl
preliminary data sheet dpl 4519g micronas 17 table 3C5: list of dpl 4519g write registers write register address (hex) bits description and adjustable range reset see page i 2 c subaddress = 10 hex ; registers are not readable modus 00 30 [15:0] i 2 s options, d_ctr_i/o modes 00 00 19 i2s configuration 00 40 [15:0] configuration of i 2 s format 00 00 20 i 2 c subaddress = 12 hex ; registers are all readable by using i 2 c subaddress = 13 hex volume main channel 00 00 [15:8] [ + 12 db ... - 114 db, mute] mute 24 [7:5] [4:0] 1/8 db steps must be set to 0 000 bin 00000 bin balance main channel [l/r] 00 01 [15:8] [0...100 / 100% and 100 / 0...100%] [ - 127...0 / 0 and 0 / - 127...0 db] 100%/100% 25 balance mode main [7:0] [linear / logarithmic mode] linear mode bass main channel 00 02 [15:8] [ + 20 db ... - 12 db] 0 db 26 treble main channel 00 03 [15:8] [ + 15 db ... - 12 db] 0 db 27 loudness main channel 00 04 [15:8] [0 db ... + 17 db] 0 db 28 loudness filter characteristic [7:0] [normal, super_bass] normal volume aux channel 00 06 [15:8] [ + 12 db ... - 114 db, mute] mute 24 [7:5] [4:0] 1/8 db steps must be set to 0 000 bin 00000 bin volume scart1 output channel 00 07 [15:8] [ + 12 db ... - 114 db, mute] mute 29 main source select 00 08 [15:8] [i 2 s1, i 2 s2, i 2 s3 ch1&2, i 2 s3 ch3&4,...] undefined 23 main channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 23 aux source select 00 09 [15:8] [i 2 s1, i 2 s2, i 2 s3 ch1&2, i 2 s3 ch3&4,...] undefined 23 aux channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 23 scart1 source select 00 0a [15:8] [i 2 s1, i 2 s2, i 2 s3 ch1&2, i 2 s3 ch3&4,...] undefined 23 scart1 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 23 i 2 s source select 00 0b [15:8] [i 2 s1, i 2 s2, i 2 s3 ch1&2, i 2 s3 ch3&4,...] undefined 23 i 2 s channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 23 prescale i 2 s3 00 11 [15:8] [00 hex ... 7f hex ]10 hex 21 prescale i 2 s2 00 12 [15:8] [00 hex ... 7f hex ]10 hex 21 acb: scart switches a. d_ctr_i/o 00 13 [15:0] bits [15:0] 00 hex 30 beeper 00 14 [15:0] [00 hex ... 7f hex ]/[00 hex ... 7f hex ] 00/00 hex 30 prescale i 2 s1 00 16 [15:8] [00 hex ... 7f hex ]10 hex 21 mode tone control 00 20 [15:8] [bass/treble, equalizer] bass/treb 26 equalizer main ch. band 1 00 21 [15:8] [ + 12 db ... - 12 db] 0 db 27 equalizer main ch. band 2 00 22 [15:8] [ + 12 db ... - 12 db] 0 db 27 equalizer main ch. band 3 00 23 [15:8] [ + 12 db ... - 12 db] 0 db 27 equalizer main ch. band 4 00 24 [15:8] [ + 12 db ... - 12 db] 0 db 27 equalizer main ch. band 5 00 25 [15:8] [ + 12 db ... - 12 db] 0 db 27 subwoofer level adjust 00 2c [15:8] [0 db ... - 30 db, mute] 0 db 29
dpl 4519g preliminary data sheet 18 micronas balance aux channel [l/r] 00 30 [15:8] [0...100 / 100% and 100 / 0...100%] [ - 127...0 / 0 and 0 / - 127...0 db] 100 %/100 % 25 balance mode aux [7:0] [linear mode / logarithmic mode] linear mode bass aux channel 00 31 [15:8] [ + 20 db ... - 12 db] 0 db 26 treble aux channel 00 32 [15:8] [ + 15 db ... - 12 db] 0 db 27 loudness aux channel 00 33 [15:8] [0 db ... + 17 db] 0 db 28 loudness filter characteristic [7:0] [normal, super_bass] normal i 2 s3 resorting 00 36 [15:8] through, straight eight, l/r eight, l/r six, l/r four, 2ch through 00 hex 22 surround source select 00 48 [15:8] [i 2 s1, i 2 s2, i 2 s3 ch1&2, i 2 s3 ch3&4,...] undefined 23 surround channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 23 spatial effect for surround processing 00 49 [15:8] [0% - 100%] 00 hex 31 virtual surround effect strength 00 4a [15:8] [0% - 100%] 00 hex 31 decoder matrix 00 4b [15:8] [adaptive/passive/effect] 00 hex 32 surround reproduction [7:4] [rear_speaker/front_speaker/panorama/ 3d_panorama] 0 hex 32 center mode [3:0] [phantom/normal/wide/off] 0 hex 32 surround delay 00 4c [15:0] [5...31ms] 00 hex 32 noise generator 00 4d [15:0] [noisel, noisec, noiser, noises] 00 hex 32 table 3C6: list of dpl 4519g read registers read register address (hex) bits description and adjustable range see page i 2 c subaddress = 11 hex ; registers are not writable status 02 00 [15:0] monitoring of settings e.g. d_ctr_i/o 21 i 2 c subaddress = 13 hex ; registers are not writable dpl hardware version code 00 1e [15:8] [00 hex ... ff hex ]33 dpl major revision code [7:0] [00 hex ... ff hex ]33 dpl product code 00 1f [15:8] [00 hex ... ff hex ]33 dpl rom version code [7:0] [00 hex ... ff hex ]33 table 3C5: list of dpl 4519g write registers, continued write register address (hex) bits description and adjustable range reset see page
preliminary data sheet dpl 4519g micronas 19 3.3.2. description of user registers 3.3.2.1. write registers on i 2 c subaddress 10 hex table 3C7: write registers on i 2 c subaddress 10 hex register address function name modus 00 30 hex modus register bit[15:8] 0 undefined, must be 0 bit[7] 0/1 active/tristate state of audio clock output pin aud_cl_out bit[6] word strobe alignment (synchronous i 2 s) 0 ws changes at data word boundary 1 ws changes one clock cycle in advance bit[5] 0/1 master/slave mode of i 2 s interface bit[4] 0/1 active/tristate state of i 2 s output pins bit[3] state of digital output pins d_ctr_i/o_0 and _1 0 active: d_ctr_i/o_0 and _1 are output pins (can be set by means of the acb register) 1 tristate: d_ctr_i/o_0 and _1 are input pins (level can be read out of status[4,3]) bit[2:0] 0 undefined, must be 0 modus
dpl 4519g preliminary data sheet 20 micronas i2s configuration 00 40 hex i2s configuration register i2s3 1) bit[11] i 2 s data alignment (must be 0 if bit[2] = 1) 0/1 left/right aligned bit[10] wordstrobe polarity (must be 0 if bit[2] = 1) 1 0 = right, 1 = left 0 1 = right, 0 = left bit[9] wordstrobe alignment (asynchronous i2s_3) 0 ws changes at data word boundary 1 ws changes one clock cycle in advance bit[8] sample mode 0/1 two/multi sample bit[7:4] word length of each data packet = (n - 2)/2 bit[3]=0, bit[8]=1 (multi-sample input mode) 0111 16 bit 1000 18 bit ... 1111 32 bit bit[3]=0, bit[8]=0 (two-sample input mode) xxxx 16...32 bit, 18-bit valid bit[3]=1, bit[8]=1 (multi-sample output mode) 1111 32 bit bit[3]=1, bit[8]=0 (two-sample output mode) 0111 16 bit 1111 32 bit bit[3] i 2 s3 mode 1 output (i2s3 cl/ws active) 0 input (i2s3 cl/ws tristate) i 2 s1/2/3 bit[2] i 2 s1/2/3 timing 1i 2 s3 timing for all i 2 s inputs (1/2/3) 0 default mode i 2 s out bit[1:0] i2s_cl frequency and i2s_da_out sample length 00 2 * 16 bit (1.536 mhz clk) 01 2 * 32 bit (3.072 mhz clk) 10 8 * 32 bit (12.288 mhz clk) i2s_config i2s3_align i2s3_ws_pol i2s3_ws_mode i2s3_msamp i2s3_mbit i2s3_mode i2s_timing 1) i2s_cl3 frequency depends on bit[8] and bits[7:4] as follows: [8] = 0, [7:4] = 0111 f = fs*(2*16) [8] = 0, [7:4] = else f = fs*(2*32) [8] = 1 f = fs*(8*32) table 3C7: write registers on i 2 c subaddress 10 hex , continued register address function name
preliminary data sheet dpl 4519g micronas 21 3.3.2.2. read registers on i 2 c subaddress 11 hex 3.3.2.3. write registers on i 2 c subaddress 12 hex table 3C8: read registers on i 2 c subaddress 11 hex register address function name 02 00 hex status register contains the status of the d_ctr_i/o pins bit[15:5] undefined bit[4] 0/1 low/high level of digital i/o pin d_ctr_i/o_1 bit[3] 0/1 low/high level of digital i/o pin d_ctr_i/o_0 bit[2:0] undefined status table 3C9: write registers on i 2 c subaddress 12 hex register address function name preprocessing 00 16 hex 00 12 hex 00 11 hex i2s1 prescale i2s2 prescale i2s3 prescale defines the prescale value for digital i 2 s input signals bit[15:8] 00 hex off 10 hex 0 db gain (recommendation) 7f hex + 18 db gain (maximum gain) pre_i2s1 pre_i2s2 pre_i2s3
dpl 4519g preliminary data sheet 22 micronas i2s3 resorting matrix 00 36 hex i2s3 resorting matrix (not mentioned bit combinations must not be used) resorting of multichannel inputs bit[15:8] 0000 hex : 8 channel, through 1,2,3,4,5,6,7,8 ? 1,2,3,4,5,6,7,8 l t ,r t ? l t ,r t ,--,--,--,--,--,-- l t ,r t ,l virtual ,r virtual ? l t ,r t ,l virtual ,r virtual ,--,--,--,-- 0001 hex : 8 channel, straight eight 1,2,3,4,5,6,7,8 ? 7,8,1,2,3,4,5,6 l,r,s l ,s r ,c,lfe,l t ,r t ? l t ,r t ,l,r,s l ,s r ,c,lfe 0002 hex : 8 channel, left/right eight, mas 3528e 1,2,3,4,5,6,7,8 ? 4,8,1,5,2,6,3,7 l,s l ,c,l t ,r,s r ,lfe,r t ? l t ,r t ,l,r,s l ,s r ,c,lfe 0003 hex : 6 channel, left/right six 1,2,3,4,5,6 ? -,-,1,4,2,5,3,6 l,s l ,c,r,s r ,lfe ? --,--,l,r,s l ,s r ,c,lfe 0004 hex : 4 channel, left/right four, external prologic 1,2,3,4 ? -,-,1,3,4,4,2,- l,c,r,s ? --,--,l,r,s l ,s r ,c,-- 0010 hex : 2 channel, through; internal prologic 1,2 ? 1,2,+,+,+,+,+,+ l t ,r t ? l t ,r t ,l pl ,r pl ,s pl ,s pl ,c pl ,sub pl +: channel will be replaced by internally generated signal x pl : internally generated signal i2s3_sort table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet dpl 4519g micronas 23 source select and output channel matrix 00 08 hex 00 09 hex 00 0a hex 00 0b hex 00 48 hex source for: main output aux output scart1 da output i 2 s output surround processing bit[15:8] 5 i 2 s1 input 6i 2 s2 input 7i 2 s3 input channels 1&2 (e.g. lt,rt) 1) 8i 2 s3 input channels 3&4 (e.g. l,r) 1) or pro logic processed l, r 9i 2 s3 input channels 5&6 (e.g. sl,sr) 1) or pro logic processed s, s (both channels same signal) 10 i 2 s3 input channels 7&8 (e.g. c,sub) 1) or pro logic processed c, sub 1) exemplary channel assignment in a micronas digital multichannel sound sys- tem with mas 3528e and msp 4450g. src_main src_aux src_scart1 src_i2s src_dpl 00 08 hex 00 09 hex 00 0a hex 00 0b hex 00 48 hex channel matrix for: main output aux output scart1 da output i 2 s output surround processing bit[7:0] 00 hex sound a mono (or left mono) 10 hex sound b mono (or right mono) 20 hex stereo (transparent mode) 30 hex mono (l+r)/2 usually the matrix modes should be set to stereo (transparent). mat_main mat_aux mat_scart1 mat_i2s mat_dpl table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
dpl 4519g preliminary data sheet 24 micronas main and aux processing 00 00 hex 00 06 hex volume main volume aux bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex - 1db ... 02 hex - 113 db 01 hex - 114 db 00 hex mute (reset condition) ff hex fast mute bit[7:5] higher resolution volume table 0 + 0db 1 + 0.125 db increase in addition to the volume table ... 7 + 0.875 db increase in addition to the volume table bit[4:0] not used must be set to 0 with large scale input signals, positive volume settings may lead to signal clipping. the dpl 4519g main and aux volume function is divided into a digital and an analog section. with fast mute, volume is reduced to mute position by digital volume only. analog volume is not changed. this reduces any audible dc plops. to turn volume on again, the volume step that has been used before fast mute was activated must be transmitted. vol_main vol_aux table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet dpl 4519g micronas 25 00 01 hex 00 30 hex balance main channel balance aux channel bit[15:8] linear mode 7f hex left muted, right 100% 7e hex left 0.8%, right 100% ... 01 hex left 99.2%, right 100% 00 hex left 100%, right 100% ff hex left 100%, right 99.2% ... 82 hex left 100%, right 0.8% 81 hex left 100%, right muted bit[15:8] logarithmic mode 7f hex left - 127 db, right 0 db 7e hex left - 126 db, right 0 db ... 01 hex left - 1 db, right 0 db 00 hex left 0 db, right 0 db ff hex left 0 db, right - 1db ... 81 hex left 0 db, right - 127 db 80 hex left 0 db, right - 128 db bit[3:0] balance mode 0 hex linear 1 hex logarithmic positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. bal_main bal_aux table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
dpl 4519g preliminary data sheet 26 micronas 00 20 hex tone control mode main channel bit[15:8] 00 hex bass and treble is active ff hex equalizer is active defines whether bass/treble or equalizer is activated for the main channel. bass/treble and equalizer cannot work simultaneously. if equalizer is used, bass and treble coefficients must be set to zero and vice versa. tone_mode 00 02 hex 00 31 hex bass main channel bass aux channel bit[15:8] normal range 60 hex + 12 db 58 hex + 11 db ... 08 hex + 1db 00 hex 0db f8 hex - 1db ... a8 hex - 11 db a0 hex - 12 db bit[15:8] extended range 7f hex + 20 db 78 hex + 18 db 70 hex + 16 db 68 hex + 14 db higher resolution is possible: an lsb step in the normal range results in a gain step of about 1/8 db, in the extended range about 1/4 db. with positive bass settings, internal clipping may occur even with overall volume less than 0 db. this will lead to a clipped output signal. therefore, it is not rec- ommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. bass_main bass_aux table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet dpl 4519g micronas 27 00 03 hex 00 32 hex treble main channel treble aux channel bit[15:8] 78 hex + 15 db 70 hex + 14 db ... 08 hex + 1db 00 hex 0db f8 hex - 1db ... a8 hex - 11 db a0 hex - 12 db higher resolution is possible: an lsb step results in a gain step of about 1/8 db. with positive treble settings, internal clipping may occur even with overall vol- ume less than 0 db. this will lead to a clipped output signal. therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. treb_main treb_aux 00 21 hex 00 22 hex 00 23 hex 00 24 hex 00 25 hex equalizer main channel band 1 (below 120 hz) equalizer main channel band 2 (center: 500 hz) equalizer main channel band 3 (center: 1.5 khz) equalizer main channel band 4 (center: 5 khz) equalizer main channel band 5 (above: 10 khz) bit[15:8] 60 hex + 12 db 58 hex + 11 db ... 08 hex + 1db 00 hex 0db f8 hex - 1db ... a8 hex - 11 db a0 hex - 12 db higher resolution is possible: an lsb step results in a gain step of about 1/8 db. with positive equalizer settings, internal clipping may occur even with overall volume less than 0 db. this will lead to a clipped output signal. therefore, it is not recommended to set equalizer bands to a value that, in conjunction with vol- ume, would result in an overall positive gain. equal_band1 equal_band2 equal_band3 equal_band4 equal_band5 table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
dpl 4519g preliminary data sheet 28 micronas 00 04 hex 00 33 hex loudness main channel loudness aux channel bit[15:8] loudness gain 44 hex + 17 db 40 hex + 16 db ... 04 hex + 1db 00 hex 0db bit[7:0] loudness mode 00 hex normal (constant volume at 1 khz) 04 hex super bass (constant volume at 2 khz) higher resolution of loudness gain is possible: an lsb step results in a gain step of about 1/4 db. loudness increases the volume of low- and high-frequency signals, while keep- ing the amplitude of the 1-khz reference frequency constant. the intended loud- ness has to be set according to the actual volume setting. because loudness introduces gain, it is not recommended to set loudness to a value that, in con- junction with volume, would result in an overall positive gain. the corner frequency for bass amplification can be set to two different values. in super bass mode, the corner frequency is shifted up. the point of constant vol- ume is shifted from 1 khz to 2 khz. loud_main loud_aux table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet dpl 4519g micronas 29 00 2c hex subwoofer level adjustment bit[15:8] 00 hex 0db ff hex - 1db ... e3 hex - 29 db e2 hex - 30 db ... 80 hex mute subw_level scart output channel 00 07 hex volume scart1 output channel bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex - 1db ... 02 hex - 113 db 01 hex - 114 db 00 hex mute (reset condition) bit[7:5] higher resolution volume table 0 + 0 db 1 + 0.125 db increase in addition to the volume table ... 7 + 0.875 db increase in addition to the volume table bit[4:0] 01 hex this must be 01 hex vol_scart1 table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
dpl 4519g preliminary data sheet 30 micronas scart switches and digital i/o pins 00 13 hex acb register defines the level of the digital output pins and the position of the scart switches bit[15] 0/1 low/high of digital output pin d_ctr_i/o_1 (modus[3]=0) bit[14] 0/1 low/high of digital output pin d_ctr_i/o_0 (modus[3]=0) bit[13:5] scart1 output select xx00xx x0x scart3 input to scart1 output (reset position) xx01xx x0x scart2 input to scart1 output xx10xx x0x mono input to scart1 output xx11xx x0x scart1 da to scart1 output xx01xx x1x scart1 input to scart1 output xx10xx x1x scart4 input to scart1 output xx11xx x1x mute scart1 output bit[13:5] scart2 output select 00xxxx 0xx scart1 da to scart2 output (reset position) 01xxxx 0xx scart1 input to scart2 output 10xxxx 0xx mono input to scart2 output 01xxxx 1xx scart2 input to scart2 output 10xxxx 1xx scart3 input to scart2 output 11xxxx 1xx scart4 input to scart2 output 11xxxx 0xx mute scart2 output the reset position becomes active at the time of the first write transmission on the control bus to the audio processing part. by writing to the acb register first, the reset state can be redefined. acb_reg beeper 00 14 hex beeper volume and frequency bit[15:8] beeper volume 00 hex off 7f hex maximum volume bit[7:0] beeper frequency 01 hex 16 hz (lowest) 40 hex 1khz ff hex 4khz beeper table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet dpl 4519g micronas 31 surround processing 00 49 hex spatial effects for surround processing bit[15:8] spatial effect strength 7f hex enlargement 100% 3f hex enlargement 50% ... 01 hex enlargement 1.5% 00 hex effect off bit[7:0] 00 hex must be 0 increases the perceived basewidth of the reproduced left and right front chan- nels. recommended value: 50% = 40 hex . sur_spat 00 4a hex virtual surround effect strength bit[15:8] virtual surround effect strength 7f hex effect 100% 3f hex effect 50% ... 01 hex effect 1.5% 00 hex effect off bit[7:0] 00 hex must be 0 strength of the surround effect in panorama or 3d-panorama mode. in other surround reproduction modes this value must be set to 0. recommended value: 66% = 54 hex . sur_3deff table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
dpl 4519g preliminary data sheet 32 micronas 00 4b hex surround processing mode bit[15:8] decoder matrix 00 hex adaptive (for dolby surround pro logic and virtual surround) 10 hex passive (for mss, micronas surround sound) 20 hex effect (used for special effects and monophonic signals) bit[7:4] surround reproduction 0 hex rear_speaker: the surround signal is reproduced by rear speakers. 3 hex front_speaker: the surround signal is redirected to the front channels. there is no physical rear speaker con- nected. 5 hex panorama: the surround signal is processed and redi- rected to the left and right front speakers in order to create the illusion of a virtual rear speaker, although no physical rear speaker is connected. 6 hex 3d-panorama: the surround signal is processed and redirected to the left and right front speakers in order to create the illusion of a virtual rear speaker, although no physical rear speaker is connected. bit[3:0] center mode 0 hex phantom mode (no center speaker connected) 1 hex normal mode (small center speaker) 2 hex wide mode (large center speaker) 3 hex off mode (center output of the surround decoder is discarded. useful only in special effect modes) sur_mode dec_mat sur_repro c_mode 00 4c hex surround delay bit[15:8] 05 hex 5 ms delay in surround path (lowest) 06 hex 6 ms delay in surround path ... 1f hex 31 ms delay in surround path (highest)) bit[7:0] 00 hex must be 0 for dolby surround pro logic designs, only 20 ms fixed or 15-30 ms variable delay must be used. this register has no effect in 3d-panorama and pan- orama mode. sur_delay 00 4d hex noise generator bit[15:8] 00 hex noise generator off 80 hex noise generator on bit[7:0] a0 hex noise on left channel b0 hex noise on center channel c0 hex noise on right channel d0 hex noise on surround channel determines the active channel for the noise generator. sur_noise table 3C9: write registers on i 2 c subaddress 12 hex , continued register address function name
preliminary data sheet dpl 4519g micronas 33 3.3.2.4. read registers on i 2 c subaddress 13 hex table 3C10: read registers on i 2 c subaddress 13 hex register address function name dpl 4519g version readout registers 00 1e hex dpl hardware version code bit[15:8] 01 hex dpl 4519g- a 1 a change in the hardware version code defines hardware optimizations that may have influence on the chips behavior. the readout of this register is iden- tical to the hardware version code in the chips imprint. dpl_hard dpl family code bit[7:4] 3 hex dpl 45 19g-a1 dpl_family dpl major revision code bit[3:0] 7 hex dpl 4519 g -a1 dpl_revision 00 1f hex dpl product code bit[15:8] 13 hex dpl 45 19 g - a1 by means of the dpl-product code, the control processor is able to decide which tv sound standards have to be considered. dpl rom version code bit[7:0] 41 hex dpl 4519g - a 1 42 hex dpl 4519g - a 2 a change in the rom version code defines internal software optimizations, that may have influence on the chips behavior, e.g. new features may have been included. while a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new dpl 4519g versions according to this number. dpl_product dpl_rom
dpl 4519g preliminary data sheet 34 micronas 3.4. programming tips this section describes the preferred method for initial- izing the dpl 4519g. the initialization is grouped into four sections: analog signal path, input processing for i 2 s, and output processing. see fig. 2C1 on page 7 for a complete signal flow. scart signal path 1. select the source for each analog scart output with the acb register. i 2 s inputs 1. select preferred prescale for i 2 s inputs (set to 0 db after reset). 2. select i2s3 resorting matrix according to the chan- nel order of your decoding device (e.g. for mas 3528e chose mode 02 hex ) output channels 1. select the source channel and matrix for each out- put. 2. set audio baseband features 3. select volume for each output. 3.5. examples of minimum initialization codes initialization of the dpl 4519g according to these list- ings reproduces sound of the selected standard on the main output. all numbers are hexadecimal. the exam- ples have the following structure: 1. perform an i 2 c controlled reset of the ic. 2. write modus register 3. set source selection for main channel (with matrix set to stereo). 4. set volume main channel to 0 db. 3.5.1. micronas dolby digital chipset (with mas 3528e) <84008000> // softreset <84000000> <841000300020> // modus-register: i2s slave <8410004001f2> // i2s-config-register <841200360002> // i2s3 resorting matrix, mode 2 <8412000b0720> // source sel. i2s_out = i2s3 - l t /r t <841200080820> // source sel. main_out = i2s3 - l/r <841200007300> // main volume 0 db
preliminary data sheet dpl 4519g micronas 35 4. specifications 4.1. outline dimensions fig. 4C1: 80-pin plastic quad flat pack (pqfp80) weight approximately 1.61 g dimensions in mm fig. 4C2: 64-pin plastic low-profile quad flat pack (plqfp64) weight approximately 0.35 g dimensions in mm 15 x 0.8 = 12.0 0.1 0.8 0.8 41 64 24 1 65 80 40 25 0.1 3 0.2 spgs705000-3(p80)/1e 23.2 0.15 17.2 0.15 20 0.1 14 0.1 23 x 0.8 = 18.4 0.1 0.17 0.04 0.37 0.04 1.3 0.05 2.7 0.1 10 0.1 1.75 1.75 49 64 116 17 32 33 48 d0025/3e 0.5 0.5 0.1 12 0.2 1.5 0.1 1.4 0.05 12 0.2 10 0.1 0.145 0.055 0.22 0.05 15 x 0.5 = 7.5 0.1 15 x 0.5 = 7.5 0.1
dpl 4519g preliminary data sheet 36 micronas fig. 4C3: 64-pin plastic shrink dual-inline package (psdip64) weight approximately 9.0 g dimensions in mm 132 33 64 57.7 0.1 0.8 0.2 3.8 0.1 3.2 0.2 1.778 1 0.05 31 x 1.778 = 55.1 0.1 0.48 0.06 20.3 0.5 0.28 0.06 18 0.05 19.3 0.1 spgs703000-1(p64)/1e
preliminary data sheet dpl 4519g micronas 37 4.2. pin connections and short descriptions nc = not connected ( leave vacant for future compatibility reasons) tp = test pin ( leave vacant - pin is used for production test only) lv = leave vacant x = obligatory; connect as described in application circuit diagram ahvss: connect to ahvss pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin psdip 64-pin 1 64 8 nc lv not connected 219i2c_cl in/outx i 2 c clock 3 2 10 i2c_da in/out x i 2 c data 4 3 11 i2s_cl in/out lv i 2 s clock 5 4 12 i2s_ws in/out lv i 2 s word strobe 6 5 13 i2s_da_out out lv i 2 s data output 7 6 14 i2s_da_in1 in lv i 2 s1 data input 8 7 15 tp lv test pin 9 8 16 tp lv test pin 10 9 17 tp lv test pin 11 -- dvsup x digital power supply + 5 v 12 -- dvsup x digital power supply + 5 v 13 10 18 dvsup x digital power supply + 5 v 14 -- dvss x digital ground 15 -- dvss x digital ground 16 11 19 dvss x digital ground - 12 20 i2s_da_in2/3 in lv i 2 s2/3-data input 17 -- i2s_da_in2 in lv pqfp80: pin 22 separate i2s_da_in3 18 13 21 nc lv not connected 19 14 22 i2s_cl3 in lv i 2 s3 clock 20 15 23 i2s_ws3 in lv i 2 s3 word strobe 21 16 24 resetq in x power-on-reset 22 -- i2s_da_in3 in lv i 2 s3-data input 23 -- nc lv not connected 24 17 25 daca_r out lv aux out, right 25 18 26 daca_l out lv aux out, left
dpl 4519g preliminary data sheet 38 micronas 26 19 27 vref2 x reference ground 2 27 20 28 dacm_r out lv loudspeaker out, right 28 21 29 dacm_l out lv loudspeaker out, left 29 22 30 nc lv not connected 30 23 31 dacm_sub out lv subwoofer output 31 24 32 nc lv not connected 32 -- nc lv not connected 33 25 33 sc2_out_r out lv scart output 2, right 34 26 34 sc2_out_l out lv scart output 2, left 35 27 35 vref1 x reference ground 1 36 28 36 sc1_out_r out lv scart output 1, right 37 29 37 sc1_out_l out lv scart output 1, left 38 30 38 capl_a x volume capacitor aux 39 31 39 ahvsup x analog power supply 8.0 v 40 32 40 capl_m x volume capacitor main 41 -- nc lv not connected 42 -- nc lv not connected 43 -- ahvss x analog ground 44 33 41 ahvss x analog ground 45 34 42 agndc x analog reference voltage 46 -- nc lv not connected 47 35 43 sc4_in_l in lv scart 4 input, left 48 36 44 sc4_in_r in lv scart 4 input, right 49 37 45 asg ahvss analog shield ground 50 38 46 sc3_in_l in lv scart 3 input, left 51 39 47 sc3_in_r in lv scart 3 input, right 52 40 48 asg ahvss analog shield ground 53 41 49 sc2_in_l in lv scart 2 input, left 54 42 50 sc2_in_r in lv scart 2 input, right 55 43 51 asg ahvss analog shield ground 56 44 52 sc1_in_l in lv scart 1 input, left pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin psdip 64-pin
preliminary data sheet dpl 4519g micronas 39 57 45 53 sc1_in_r in lv scart 1 input, right 58 46 54 nc lv not connected 59 -- nc lv not connected 60 47 55 mono_in in lv mono input 61 -- avss x analog ground 62 48 56 avss x analog ground 63 -- nc lv not connected 64 -- nc lv not connected 65 -- avsup x analog power supply + 5v 66 49 57 avsup x analog power supply + 5v 67 50 58 nc lv not connected 68 51 59 nc lv not connected 69 52 60 nc lv not connected 70 53 61 testen in avss test pin 71 54 62 xtal_in in x crystal oscillator 72 55 63 xtal_out out x / lv crystal oscillator (see also 4.3. pin descriptions) 73 56 64 tp lv test pin 74 57 1 aud_cl_out out lv audio clock output (18.432 mhz) - -- nc lv not connected 75 58 2 nc lv not connected 76 59 3 nc lv not connected 77 60 4 d_ctr_i/o_1 in/out lv d_ctr_i/o_1 78 61 5 d_ctr_i/o_0 in/out lv d_ctr_i/o_0 79 62 6 adr_sel in x i 2 c bus address select 80 63 7 standbyq in x stand-by (low-active) pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin psdip 64-pin
dpl 4519g preliminary data sheet 40 micronas 4.3. pin descriptions pin numbers refer to the 80-pin pqfp package pin 1, nc C pin not connected. pin 2, i2c_cl C i 2 c clock input/output (fig. 4C8) via this pin, the i 2 c-bus clock signal has to be sup- plied. the signal can be pulled down by the dpl in case of wait conditions. pin 3, i2c_da C i 2 c data input/output (fig. 4C8) via this pin, the i 2 c-bus data is written to or read from the dpl. pin 4, i2s_cl C i 2 s clock input/output (fig. 4C11) clock line for the i 2 s bus. in master mode, this line is driven by the dpl; in slave mode, an external i 2 s clock has to be supplied. pin 5, i2s_ws C i 2 s word strobe input/output (fig. 4C11) word strobe line for the i 2 s bus. in master mode, this line is driven by the dpl; in slave mode, an external i 2 s word strobe has to be supplied. pin 6, i2s_da_out1 C i 2 s data output (fig. 4C7) output of digital serial sound data of the dpl on the i 2 s bus. pin 7, i2s_da_in1 C i 2 s data input 1 (fig. 4C9) first input of digital serial sound data to the dpl via the i 2 s bus. pin 8, 9, 10, tp C test pins pins 11, 12, 13, dvsup* C digital supply voltage power supply for the digital circuitry of the dpl. must be connected to a power supply. pins 14, 15, 16, dvss* C digital ground ground connection for the digital circuitry of the dpl. pin 17, i2s_da_in2 C i 2 s data input 2 (fig. 4C9) second input of digital serial sound data to the dpl via the i 2 s bus. in all packages except pqfp-80-pin this pin is also connected to the asynchronous i 2 s inter- face 3. pins 18, nc C pin not connected. pins 19, i2s_cl3 C i 2 s clock input (fig. 4C9) clock line for the i 2 s bus. since only a slave mode is available an external i 2 s clock has to be supplied. pins 20, i2s_ws3 C i 2 s word strobe input (fig. 4C9) word strobe line for the i 2 s bus. since only a slave mode is available an external i 2 s word strobe has to be supplied. pin 21, resetq C reset input (fig. 4C9) in the steady state, high level is required. a low level resets the dpl 4519g. pin 22, i2s_da_in3 C i 2 s data input 3 (fig. 4C9) asynchronous input of digital serial sound data to the dpl via the i 2 s bus. pins 23, nc C pin not connected. pins 24, 25, daca_r/l C aux outputs (fig. 4C16) output of the aux signal. a 1 nf capacitor to ahvss must be connected to these pins. the dc offset on these pins depends on the selected aux volume. pin 26, vref2 C reference ground 2 reference analog ground. this pin must be connected separately to ground (ahvss). vref2 serves as a clean ground and should be used as the reference for analog connections to the main and aux outputs. pins 27, 28, dacm_r/l C main outputs (fig. 4C16) output of the main signal. a 1 nf capacitor to ahvss must be connected to these pins. the dc offset on these pins depends on the selected main volume. pin 29 nc C pin not connected. pin 30, dacm_sub C subwoofer output (fig. 4C16) output of the subwoofer signal. a 1-nf capacitor to ahvss must be connected to this pin. due to the low frequency content of the subwoofer output, the value of the capacitor may be increased for better suppres- sion of high-frequency noise. the dc offset on this pin depends on the selected main volume. pins 31, 32 nc C pin not connected. pins 33, 34, sc2_out_r/l C scart2 outputs (fig. 4C18) output of the scart2 signal. connections to these pins must use a 100- w series resistor and are intended to be ac-coupled. pin 35, vref1 C reference ground 1 reference analog ground. this pin must be connected separately to ground (ahvss). vref1 serves as a clean ground and should be used as the reference for analog connections to the scart outputs. pins 36, 37, sc1_out_r/l C scart1 outputs (fig. 4C18) output of the scart1 signal. connections to these pins must use a 100- w series resistor and are intended to be ac-coupled.
preliminary data sheet dpl 4519g micronas 41 pin 38, capl_a C volume capacitor aux (fig. 4C13) a 10- m f capacitor to ahvsup must be connected to this pin. it serves as a smoothing filter for volume changes in order to suppress audible plops. the value of the capacitor can be lowered to 1- m f if faster response is required. the area encircled by the trace lines should be minimized; keep traces as short as possible. this input is sensitive for magnetic induction. pin 39, ahvsup* C analog power supply high volt- age power is supplied via this pin for the analog circuitry of the dpl. this pin must be connected to the + 8 v sup- ply. (+5 v-operation is possible with restrictions in per- formance) pin 40, capl_m C volume capacitor loudspeakers (fig. 4C13) a 10- m f capacitor to ahvsup must be connected to this pin. it serves as a smoothing filter for volume changes in order to suppress audible plops. the value of the capacitor can be lowered to 1 m f if faster response is required. the area encircled by the trace lines should be minimized; keep traces as short as possible. this input is sensitive for magnetic induction. pins 41, 42, nc C pins not connected. pins 43, 44, ahvss* C ground for analog power sup- ply high voltage ground connection for the analog circuitry of the dpl. pin 45, agndc C internal analog reference voltage this pin serves as the internal ground connection for the analog circuitry. it must be connected to the vref pins with a 3.3- m f and a 100-nf capacitor in parallel. this pins shows a dc level of typically 3.73 v. pin 46, nc C pin not connected. pins 47, 48, sc4_in_l/r C scart4 inputs (fig. 4C15) the analog input signal for scart4 is fed to this pin. analog input connection must be ac-coupled. pin 49, asg* C analog shield ground analog ground (ahvss) should be connected to this pin to reduce cross-coupling between scart inputs. pins 50, 51, sc3_in_l/r C scart3 inputs (fig. 4C15) the analog input signal for scart3 is fed to this pin. analog input connection must be ac-coupled. pin 52, asg* C analog shield ground analog ground (ahvss) should be connected to this pin to reduce cross-coupling between scart inputs. pins 53, 54 sc2_in_l/r C scart2 inputs (fig. 4C15) the analog input signal for scart2 is fed to this pin. analog input connection must be ac-coupled. pin 55, asg* C analog shield ground analog ground (ahvss) should be connected to this pin to reduce cross-coupling between scart inputs. pins 56, 57 sc1_in_l/r C scart1 inputs (fig. 4C15) the analog input signal for scart1 is fed to this pin. analog input connection must be ac-coupled. pin 58, nc C pin not connected pin 59, nc C pin not connected. pin 60 mono_in C mono input (fig. 4C15) the analog mono input signal is fed to this pin ac-cou- pled. pins 61, 62, avss* C analog power supply voltage ground connection for the analog if input circuitry of the dpl. pins 63, 64, nc C pins not connected. pins 65, 66, avsup* C analog power supply voltage power is supplied via this pin for the analog if input cir- cuitry of the dpl. this pin must be connected to the + 5v supply. pin 67, 68, 69, nc C pin not connected. pin 70, testen C test enable pin (fig. 4C9) this pin enables factory test modes. for normal opera- tion, it must be connected to ground. pins 71, 72 xtal_in, xtal_out C crystal input and output pins (fig. 4C12) these pins are connected to an 18.432 mhz crystal oscillator which is digitally tuned by integrated capaci- tances. an external clock can be fed into xtal_in (leave xtal_out vacant in this case). the audio clock output signal aud_cl_out is derived from the oscillator. external capacitors at each crystal pin to ground (avss) are required. it should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. pin 73, tp C this pin is needed for factory tests. for normal operation, it must be left vacant. pin 74, aud_cl_out C audio clock output (fig. 4C12) this is the 18.432 mhz main clock output. pins 75, 76, nc C pins not connected. pins 77, 78, d_ctr_i/o_1/0 C digital control input/ output pins (fig. 4C11) general purpose input/output pins.
dpl 4519g preliminary data sheet 42 micronas pin 79, adr_sel C i 2 c bus address select (fig. 4C10) this pin selects the device address for the dpl. (see table 3C1). pin 80, standbyq C stand-by in normal operation, this pin must be high. if the dpl is switched to stand-by-mode , the scart switches maintain their position and function. (see section 2.7.2.) * application note: all ground pins should be connected to one low-resis- tive ground plane. all supply pins should be connected separately with short and low-resistive lines to the power supply. decoupling capacitors from dvsup to dvss, avsup to avss, and ahvsup to ahvss are recommended as closely as possible to these pins. decoupling of dvsup and dvss is most important. we recommend using more than one capacitor. by choosing different values, the frequency range of active decoupling can be extended. in our application boards we use: 220 pf, 470 pf, 1.5 nf, and 10 m f. the capacitor with the low- est value should be placed nearest to the pins. the asg pins should be connected as closely as pos- sible to the ic ground. they are intended for leading with the scart signals as shield lines and should not be connected to ground at the scart-connector again.
preliminary data sheet dpl 4519g micronas 43 4.4. pin configurations fig. 4C4: 80-pin pqfp package 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 101112131415161718192021222324 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 avsup avsup nc nc nc testen xtal_in xtal_out tp aud_cl_out nc nc d_ctr_i/o_1 d_ctr_i/o_0 adr_sel standbyq capl_m ahvsup capl_a sc1_out_l sc1_out_r vref1 sc2_out_l sc2_out_r nc nc dacm_sub nc dacm_l dacm_r vref2 daca_l nc avss avss mono_in nc nc sc1_in_r sc1_in_l asg nc sc2_in_r sc2_in_l asg sc3_in_r sc3_in_l asg sc4_in_r sc4_in_l nc agndc ahvss ahvss nc nc i2c_cl i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 nc nc nc nc dvsup dvsup dvsup dvss dvss dvss i2s_da_in2 nc i2s_cl3 i2s_ws3 resetq i2s_da_in3 nc daca_r dpl 4519g
dpl 4519g preliminary data sheet 44 micronas fig. 4C5: 64-pin plqfp package 49 avsup 50 nc 51 nc 52 nc 53 testen 54 xtal_in 55 xtal_out 56 tp 57 aud_cl_out 58 nc 59 nc 60 d_ctr_i/o_1 61 c_ctr_i/o_0 62 adr_sel 63 standbyq 64 nc capl_m 32 ahvsup 31 capl_a 30 sc1_out_l 29 sc1_out_r 28 vref1 27 sc2_out_l 26 sc2_out_r 25 nc 24 dacm_sub 23 nc 22 dacm_l 21 dacm_r 20 vref2 19 daca_l 18 daca_r 17 mono_in nc sc1_in_r sc1_in_l asg sc2_in_r sc2_in_l avss asg sc3_in_r sc3_in_l asg sc4_in_r sc4_in_l agndc ahvss i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 tp tp i2c_cl tp dvsup dvss i2s_da_in2/3 nc i2s_cl3 i2s_ws3 resetq 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dpl 4519g
preliminary data sheet dpl 4519g micronas 45 fig. 4C6: 64-pin psdip package 4.5. pin circuits pin numbers refer to the pqfp80 package. fig. 4C7: output pin 6 (i2s_da_out) fig. 4C8: input/output pins 2 and 3 (i2c_cl, i2c_da) fig. 4C9: input pins 7, 17, 21, 22, 70, and 80 (i2s_da_in1..3, resetq, testen, standbyq ) fig. 4C10: input pin 79 (adr_sel) 1 aud_cl_out 2 nc 3 nc 4 d_ctr_i/o_1 5 d_ctr_i/o_0 6 adr_sel 7 standbyq 8 nc 9 i2c_cl 10 i2c_da 11 i2s_cl 12 i2s_ws 13 i2s_da_out 14 i2s_da_in1 15 tp 16 tp tp 64 xtal_out 63 xtal_in 62 testen 61 nc 60 nc 59 nc 58 avsup 57 avss 56 mono_in 55 nc 54 sc1_in_r 53 sc1_in_l 52 asg 51 sc2_in_r 50 sc2_in_l 49 17 tp 18 dvsup 19 dvss 20 i2s_da_in2/3 21 nc 22 i2s_cl3 23 i2s_ws3 24 resetq 25 daca_r 26 daca_l asg 48 sc3_in_r 47 sc3_in_l 46 asg 45 sc4_in_r 44 sc4_in_l 43 agndc 42 ahvss 41 capl_m 40 ahvsup 39 dpl 4519g vref2 dacm_r dacm_l nc dacm_sub nc 38 37 36 35 34 33 27 28 29 30 31 32 capl_a sc1_out_l sc1_out_r vref1 sc2_out_l sc2_out_r dvsup p n gnd n gnd adr_sel gnd dvsup 23 k w 23 k w
dpl 4519g preliminary data sheet 46 micronas fig. 4C11: input/output pins 4, 5, 77, and 78 (i2s_cl, i2s_ws, d_ctr_i/o_1, d_ctr_i/o_0) fig. 4C12: output/input pins 71, 72, and 74 (xtalin, xtalout, aud_cl_out) fig. 4C13: capacitor pins 38 and 40 (capl_a, capl_m) fig. 4C14: input pin 60 (mono_in ) fig. 4C15: input pins 47, 48, 50, 51, 53, 54, 56, and 57 (sc4-1_in_l/r) fig. 4C16: output pins 24, 25, 27, 28 and 30 (daca_r/l, dacm_r/l, dacm_sub) fig. 4C17: pin 45 (agndc) fig. 4C18: output pins 33, 34, 36, and 37 (sc_2_out_r/l, sc_1_out_r/l) dvsup p n gnd 3 - 30 pf 2.5 v 500 k w 3 - 30 pf p n gain=0.5 0...2 v ? 3.75 v 24 k w ? 3.75 v 40 k w ahvsup 0...1.2 ma 3.3 k w ? 3.75 v 125 k w 26 pf 120 k w 300 w ? 3.75 v
preliminary data sheet dpl 4519g micronas 47 4.6. electrical characteristics 4.6.1. absolute maximum ratings stresses beyond those listed in the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions/characteristics of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. symbol parameter pin name min. max. unit t a ambient operating temperature - 070 1) c t s storage temperature -- 40 125 c v sup1 first supply voltage ahvsup - 0.3 9.0 v v sup2 second supply voltage dvsup - 0.3 6.0 v v sup3 third supply voltage avsup - 0.3 6.0 v dv sup23 voltage between avsup and dvsup avsup, dvsup - 0.5 0.5 v p tot package power dissipation psdip64 pqfp80 plqfp64 1300 1000 960 1) mw v idig input voltage, all digital inputs - 0.3 v sup2 +0.3 v i idig input current, all digital pins -- 20 +20 ma 2) v iana input voltage, all analog inputs scn_in_s, 3) mono_in - 0.3 v sup1 +0.3 v i iana input current, all analog inputs scn_in_s, 3) mono_in - 5+5ma 2) i oana output current, all scart outputs scn_out_s 3) 4) , 5) 4) , 5) i oana output current, all analog outputs except scart outputs dacp_s 3) 4) 4) i cana output current, other pins connected to capacitors capl_p, 3) agndc 4) 4) 1) plqfp64: 65 c 2) positive value means current flowing into the circuit 3) n means 1, 2, 3, or 4, s means l or r, p means m or a 4) the analog outputs are short circuit proof with respect to first supply voltage and ground. 5) total chip power dissipation must not exceed absolute maximum rating.
dpl 4519g preliminary data sheet 48 micronas 4.6.2. recommended operating conditions (t a = 0 to 70 c) 4.6.2.1. general recommended operating conditions 4.6.2.2. analog input and output recommendations symbol parameter pin name min. typ. max. unit v sup1 first supply voltage (8-v operation) ahvsup 7.6 8.0 8.7 v first supply voltage (5-v operation) 4.75 5.0 5.25 v v sup2 second supply voltage dvsup 4.75 5.0 5.25 v v sup3 third supply voltage avsup 4.75 5.0 5.25 v t stbyq1 standbyq setup time before turn-off of second supply voltage standbyq, dvsup 1 m s symbol parameter pin name min. typ. max. unit c agndc agndc-filter-capacitor agndc - 20% 3.3 m f ceramic capacitor in parallel - 20% 100 nf c insc dc-decoupling capacitor in front of scart inputs scn_in_s 1) - 20% 330 nf v insc scart input level 2.0 v rms v inmono input level, mono input mono_in 2.0 v rms r lsc scart load resistance scn_out_s 1) 10 k w c lsc scart load capacitance 6.0 nf c vma main/aux volume capacitor capl_m, capl_a 10 m f c fma main/aux filter capacitor dacm_s, daca_s 1) - 10% 1 + 10% nf 1) n means 1, 2, or 3, s means l or r, p means m or a
preliminary data sheet dpl 4519g micronas 49 4.6.2.3. crystal recommendations symbol parameter pin name min. typ. max. unit general crystal recommendations f p crystal parallel resonance fre- quency at 12 pf load capacitance 18.432 mhz r r crystal series resistance 8 25 w c 0 crystal shunt (parallel) capacitance 6.2 7.0 pf c l external load capacitance 1) xtal_in, xtal_out psdip approx. 1.5 p(l)qfp approx. 3.3 pf pf crystal recommendations for master-slave applications (dpl clock must perform synchronization to i 2 s clock) f tol accuracy of adjustment - 20 + 20 ppm d tem frequency variation versus temperature - 20 + 20 ppm c 1 motional (dynamic) capacitance 19 24 ff f cl required open loop clock frequency (t amb = 25 c) aud_cl_out 18.431 18.433 mhz crystal recommendations for other applications (no synchronization to i 2 s clock possible) f tol accuracy of adjustment - 100 + 100 ppm d tem frequency variation versus temperature - 50 + 50 ppm f cl required open loop clock frequency (t amb = 25 c) aud_cl_out 18.429 18.435 mhz amplitude recommendation for operation with external clock input (c load after reset typ. 22 pf) v xca external clock amplitude xtal_in 0.7 v pp 1) external capacitors at each crystal pin to ground are required. they are necessary to tune the open-loop fre- quency of the internal pll and to stabilize the frequency in closed-loop operation. due to different layouts, the accurate capacitor size should be determined with the customer pcb . the sug- gested values (1.5...3.3 pf) are figures based on experience and should serve as start value. to define the capacitor size, reset the dpl without transmitting any further i2c telegrams. measure the fre- quency at aud_cl_out-pin. change the capacitor size until the free running frequency matches 18.432 mhz as closely as possible. the higher the capacity, the lower the resulting clock frequency.
dpl 4519g preliminary data sheet 50 micronas 4.6.3. characteristics at t a = 0 to 70 c, f clock = 18.432 mhz, v sup1 = 7.6 to 8.7 v, v sup2 = 4.75 to 5.25 v for min./max. values at t a = 60 c, f clock = 18.432 mhz, v sup1 = 8 v, v sup2 = 5 v for typical values, t j = junction temperature main (m) = main channel, aux (a) = aux channel 4.6.3.1. general characteristics symbol parameter pin name min. typ. max. unit test conditions supply i sup1a first supply current (active) (ahvsup = 8 v) ahvsup 18 12 25 17 ma ma volume main and aux 0 db volume main and aux -30 db first supply current (active) (ahvsup = 5 v) 12 8 17 11 ma ma volume main and aux 0 db volume main and aux -30 db i sup2a second supply current (active) (dvsup = 5 v) dvsup 70 85 ma i sup3a third supply current (active) avsup 9 13 ma i sup1s first supply current (ahvsup = 8 v) ahvsup 5.6 7.7 ma standby mode standbyq = low first supply current (ahvsup = 5 v) 3.7 5.1 ma clock f clock clock input frequency xtal_in 18.432 mhz d clock clock high to low ratio 45 55 % t jitter clock jitter (verification not provided in production test) 50 ps v xtaldc dc-voltage oscillator 2.5 v t startup oscillator startup time at vdd slew-rate of 1 v/ m s xtal_in, xtal_out 0.4 2 ms v aclkac audio clock output ac voltage aud_cl_out 1.2 1.8 v pp load = 40 pf v aclkdc audio clock output dc voltage 0.4 0.6 v sup3 i max = 0.2 ma r outhf_acl hf output resistance 140 w
preliminary data sheet dpl 4519g micronas 51 4.6.3.2. digital inputs, digital outputs symbol parameter pin name min. typ. max. unit test conditions digital input levels v digil digital input low voltage standbyq d_ctr_i/o_0/1 0.2 v sup2 v digih digital input high voltage 0.5 v sup2 z digi input impedance 5 pf i dleak digital input leakage current - 11 m a0v < u input < dvsup d_ctr_i/o_0/1: tri-state v digil adr_sel input low voltage adr_sel 0.2 v sup2 v digih adr_sel input high voltage 0.8 v sup2 i adrsel input current - 500 - 220 m au adr_sel = dvss 220 500 m au adr_sel = dvsup digital output levels v dctrol digital output low voltage d_ctr_i/o_0 d_ctr_i/o_1 0.4 v iddctr = 1 ma v dctroh digital output high voltage v sup2 - 0.3 v iddctr = - 1 ma
dpl 4519g preliminary data sheet 52 micronas 4.6.3.3. reset input and power-up fig. 4C19: power-up sequence symbol parameter pin name min. typ. max. unit test conditions resetq input levels v rhl reset high-low transition voltage resetq 0.3 0.4 v sup2 v rlh reset low-high transition voltage 0.45 0.55 v sup2 z res input impedance 5 pf i res input pin leakage current -1 1 m a0v < u input < dvsup v sup2 - 10% internal reset t/ms resetq avsup dvsup high low t/ms t/ms low-to-high threshold high-to-low threshold reset delay >2 ms note: the reset should not reach high level before the oscillator has started. this requires a reset delay of >2 ms 0.3 x v sup2 means 1.5 volt with v sup2 = 5.0 v 0.45 v sup2 0.3...0.4 v sup2
preliminary data sheet dpl 4519g micronas 53 4.6.3.4. i 2 c-bus characteristics fig. 4C20: i 2 c bus timing diagram symbol parameter pin name min. typ. max. unit test conditions v i2cil i 2 c-bus input low voltage i2c_cl, i2c_da 0.3 v sup2 v i2cih i 2 c-bus input high voltage 0.6 v sup2 t i2c1 i 2 c start condition setup time 120 ns t i2c2 i 2 c stop condition setup time 120 ns t i2c5 i 2 c-data setup time before rising edge of clock 55 ns t i2c6 i 2 c-data hold time after falling edge of clock 55 ns t i2c3 i 2 c-clock low pulse time i2c_cl 500 ns t i2c4 i 2 c-clock high pulse time 500 ns f i2c i 2 c-bus frequency 1.0 mhz v i2col i 2 c-data output low voltage i2c_cl, i2c_da 0.4 v i i2col = 3 ma i i2coh i 2 c-data output high leakage current 1.0 m av i2coh = 5 v t i2col1 i 2 c-data output hold time after falling edge of clock 15 ns t i2col2 i 2 c-data output setup time before rising edge of clock 100 ns f i2c = 1 mhz i2c_cl i2c_da as input i2c_da as output t i2c1 t i2c5 t i2c6 t i2c2 t i2c4 t i2c3 1/f i2c t i2col2 t i2col1
dpl 4519g preliminary data sheet 54 micronas 4.6.3.5. i 2 s-bus characteristics symbol parameter pin name min. typ. max. unit test conditions v i2sil input low voltage i2s_cl i2s_ws i2s_cl3 i2s_ws3 i2s_da_in1..3 0.2 v sup2 v i2sih input high voltage 0.5 v sup2 z i2si input impedance 5 pf i leaki2s input leakage current - 11 m a0v < u input < dvsup v i2sol i 2 s output low voltage i2s_cl i2s_ws i2s_da_out 0.4 v i i2sol = 1 ma v i2soh i 2 s output high voltage v sup2 - 0.3 vi i2soh = - 1 ma f i2sows i 2 s-word strobe output frequency i2s_ws 48.0 khz f i2socl i 2 s-clock output frequency i2s_cl 1.536 3.072 12.288 mhz r i2s10/i2s20 i 2 s-clock output high/low-ratio 0.9 1.0 1.1 synchronous i 2 s interface t s_i2s i 2 s input setup time before rising edge of clock i2s_da_in1/2 i2s_cl 12 ns for details see fig. 4C21 i 2 s timing diagram (syn- chronous interface) t h_i2s i 2 s input hold time after rising edge of clock 40 ns t d_i2s i 2 s output delay time after falling edge of clock i2s_cl i2s_ws i2s_da_out 28 ns c l =30 pf f i2sws i 2 s-word strobe input frequency i2s_ws 48.0 khz f i2scl i 2 s-clock input frequency i2s_cl 1.536 3.072 12.288 mhz r i2scl i 2 s-clock input ratio 0.9 1.1 asynchronous i 2 s interface t s_i2s3 i 2 s3 input setup time before rising edge of clock i2s_cl3 i2s_ws3 i2s_da_in3 4 ns for details see fig. 4C22 i 2 s timing diagram (asyn- chronous interface) t h_i2s3 i 2 s3 input hold time after rising edge of clock 40 ns f i2s3ws i 2 s3-word strobe input frequency i2s_ws3 5 50 khz f i2s3cl i 2 s3-clock input frequency i2s_cl3 3.2 mhz r i2s3cl i 2 s3-clock input ratio 0.9 1.1
preliminary data sheet dpl 4519g micronas 55 fig. 4C21: i 2 s timing diagram (synchronous interface) data: msb first, i 2 s synchronous master r lsb l lsb r lsb l lsb 16/32 bit right channel l lsb l lsb r msb r msb detail c i2s_ws i2s_cl i2s_da_in* ) detail a modus[6] = 1 modus[6] = 0 detail b r lsb r lsb l msb l msb i2s_da_out 16/32 bit right channel 16/32 bit left channel 16/32 bit left channel 1/f i2sws i2s_cl detail c i2s_ws as input i2s_ws as output 1/f i2scl t s_i2s t d_i2s detail a,b i2s_cl i2s_da_out t d_i2s data: msb first, i 2 s synchronous slave r lsb l lsb r lsb l lsb 16, 18...32 bit right channel l lsb l lsb r msb r msb detail c i2s_ws i2s_cl i2s_da_in* ) detail a modus[6] = 1 modus[6] = 0 detail b r lsb r lsb l msb l msb i2s_da_out 16, 18...32 bit right channel 16, 18...32 bit left channel 16,18...32 bit left channel 1/f i2sws t h_i2s t s_i2s i2s_da_in 1) note: 1) i2s_da_in can be - i2s_da_in1, - i2s_da_in2, or - i2s_da_in2/3
dpl 4519g preliminary data sheet 56 micronas fig. 4C22: i 2 s timing diagram (asynchronous interface) 4.6.3.6. analog baseband inputs and outputs, agndc symbol parameter pin name min. typ. max. unit test conditions analog ground v agndc0 agndc open circuit voltage ahvsup = 8 v ahvsup = 5 v agndc 3.8 2.5 v v r load 3 10 m w r outagn agndc output resistance ahvsup = 8 v ahvsup = 5 v 70 47 125 83 180 120 k w k w 3 v v agndc 4 v analog input resistance r insc scart input resistance from t a = 0 to 70 c scn_in_s 1) 25 40 58 k w f signal = 1 khz, i = 0.05 ma r inmono mono input resistance from t a = 0 to 70 c mono_in 152435k w f signal = 1 khz, i = 0.1 ma 1) n means 1, 2, 3, or 4; s means l or r right aligned (i 2 s_config[11] = 1, i 2 s_config[9] = 0) 16 bit data & 16...32 clocks allowed i2s_ws3 i2s_cl3 i2s_da_in3 msb 1/f i2s3ws 1/f i2s3cl i2s_cl3 i2s_da_in3 i2s_ws3 t h_i2s3 right sample (i 2 s_config[10] = 0) right sample (i 2 s_config[10] = 1) left sample (i 2 s_config[10] = 0) left sample (i 2 s_config[10] = 1) msb lsb msb msb lsb i2s_da_in3 i2s_da_in3 left aligned (i 2 s_config[9] = 0) left aligned (i 2 s_config[9] = 1) 16,18...32 bit data & clocks allowed 16,18...32 bit data & clocks allowed t s_i2s3 t s_i2s3
preliminary data sheet dpl 4519g micronas 57 audio analog-to-digital-converter v aicl analog input clipping level for analog-to-digital-conversion (ahvsup=8 v) scn_in_s, 1) mono_in 2.00 2.25 v rms f signal = 1 khz analog input clipping level for analog-to-digital-conversion (ahvsup=5 v) 1.13 1.51 v rms scart outputs r outsc scart output resistance scn_out_s 1) 200 200 330 460 500 w w f signal = 1 khz, i = 0.1 ma, t j = 27c, t a = 0 to 70c dv outsc deviation of dc-level at scart output from agndc voltage - 70 + 70 mv a sctosc gain from analog input to scart output scn_in_s, 1) mono_in ? scn_out_s 1) - 1.0 + 0.5 db f signal = 1 khz f rsctosc frequency response from analog input to scart output - 0.5 + 0.5 db with resp. to 1 khz 20 hz to 20 000 hz v outsc signal level at scart-output (ahvsup=8 v) scn_out_s 1) 1.8 1.9 2.0 v rms f signal = 1 khz full scale digital input from i 2 s signal level at scart-output (ahvsup=5 v) 1.17 1.27 1.37 v rms main and aux outputs r outma main/aux output resistance dacp_s 1) 2.1 2.1 3.3 4.6 5.0 k w k w f signal = 1 khz, i = 0.1 ma t j = 27 c from t a = 0 to 70 c v outdcma dc-level at main/aux-output (ahvsup=8 v) 1.80 2.04 61 2.28 v mv volume = 0 db volume = -30 db dc-level at main/aux-output (ahvsup=5 v) 1.12 1.36 40 1.60 v mv volume = 0 db volume = -30 db v outma signal level at main/aux-output (ahvsup=8 v) 1.23 1.37 1.51 v rms f signal = 1 khz full scale digital input from i 2 s volume = 0 db signal level at main/aux-output (ahvsup=5 v) 0.76 0.90 1.04 v rms 1) n means 1, 2, 3, or 4; s means l or r; p means m or a symbol parameter pin name min. typ. max. unit test conditions
dpl 4519g preliminary data sheet 58 micronas 4.6.3.7. power supply rejection 4.6.3.8. analog performance symbol parameter pin name min. typ. max. unit test conditions psrr: rejection of noise on ahvsup at 1 khz psrr agndc agndc 80 db from analog input to i 2 s output mono_in, scn_in_s 1) 70 db from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 70 db from i 2 s input to scart output scn_out_s 1) 60 db from i 2 s input to main/aux output dacp_s 1) 80 db 1) n means 1, 2, 3, or 4; s means l or r; p means m or a symbol parameter pin name min. typ. max. unit test conditions specifications for ahsup=8 v snr signal-to-noise ratio from analog input to i 2 s output mono_in, scn_in_s 1) 90 93 db input level = - 20 db with resp. to v aicl , f sig = 1 khz, a-weighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s 1) ? scn_out_s 1) 93 96 db input level = - 20 db, f sig = 1 khz, a-weighted 20 hz...20 khz volume = 0 db from i 2 s input to scart output scn_out_s 1) 90 93 db from i 2 s input to main/aux-output dacp_s 1) 90 93 db thd total harmonic distortion from analog input to i 2 s output mono_in, scn_in_s 1) 0.01 0.03 % input level = - 3 dbr with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s ? scn_out_s 1) 0.01 0.03 % input level = - 3 dbr, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 0.01 0.03 % from i 2 s input to main or aux out- put daca_s, dacm_s 1) 0.01 0.03 % 1) n means 1, 2, 3, or 4; s means l or r; p means m or a
preliminary data sheet dpl 4519g micronas 59 specifications for ahsup=5 v snr signal-to-noise ratio from analog input to i 2 s output mono_in, scn_in_s 1) 87 90 db input level = - 20 db with resp. to v aicl , f sig = 1 khz, a-weighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s 1) ? scn_out_s 1) 90 93 db input level = - 20 db, f sig = 1 khz, a-weighted 20 hz...20 khz volume = 0 db from i 2 s input to scart output scn_out_s 1) 87 90 db from i 2 s input to main/aux-output for analog volume at 0 db for analog volume at - 30 db dacp_s 1) 87 75 90 80 db db thd total harmonic distortion from analog input to i 2 s output mono_in, scn_in_s 1) 0.03 0.1 % input level = - 3 dbr with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s ? scn_out_s 1) 0.1 % input level = - 3 dbr, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 0.1 % from i 2 s input to main or aux out- put daca_s, dacm_s 1) 0.1 % 1) n means 1, 2, 3, or 4; s means l or r; p means m or a symbol parameter pin name min. typ. max. unit test conditions
dpl 4519g preliminary data sheet 60 micronas crosstalk specifications xtalk crosstalk attenuation input level = - 3 db, f sig = 1 khz, unused analog inputs connected to ground by z < 1 k w between left and right channel within scart input/output pair (l ? r, r ? l) scn_in ? scn_out 1) sc1_in or sc2_in ? i 2 s output sc3_in ? i 2 s output i 2 s input ? scn_out 1) 80 80 80 80 db db db db unweighted 20 hz...20 khz between left and right channel within main or aux output pair i 2 s input ? dacp 1) 75 db unweighted 20 hz...20 khz between scart input/output pairs 1) d = disturbing program o = observed program d: mono/scn_in ? scn_out o: mono/scn_in ? scn_out 1) d: mono/scn_in ? scn_out or unsel. o: mono/scn_in ? i 2 s output d: mono/scn_in ? scn_out o: i 2 s input ? scn_out 1) d: mono/scn_in ? unselected o: i 2 s input ? sc1_out 1) 100 95 100 100 db db db db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel crosstalk between main and aux output pairs i 2 s input dsp ? dacp 1) 90 db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel xtalk crosstalk from main or aux output to scart output and vice versa d = disturbing program o = observed program d: mono/scn_in/dsp ? scn_out o: i 2 s input ? dacp 1) d: mono/scn_in/dsp ? scn_out o: i 2 s input ? dacp 1) d: i 2 s input ? dacp o: mono/scn_in ? scn_out 1) d: i 2 s input ? dacm o: i 2 s input ? scn_out 1) 80 85 95 95 db db db db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel scart output load resis- tance 10 k w scart output load resis- tance 30 k w 1) n means 1, 2, 3, or 4; s means l or r; p means m or a symbol parameter pin name min. typ. max. unit test conditions
preliminary data sheet dpl 4519g micronas 61 5. appendix a: application information 5.1. phase relationship of analog outputs the analog output signals: main, aux, and scart2 all have the same phases. the scart1 output has oppo- site phase. using the i 2 s-outputs for other dsps or d/a convert- ers, care must be taken to adjust for the correct phase. fig. 5C1: phase diagram of the dpl 4519g scart1 scart1 scart2 scart4 scart3 mono main audio scart output select baseband processing aux scart1-ch. scart2 i 2 s_out1/2 i 2 s_in1/2/3 mono, scart1...4
dpl 4519g preliminary data sheet 62 micronas 5.2. application circuit sc1_out_l (37) 37 sc1_out_r (36) 36 sc2_out_l (34) 34 sc2_out_r (33) 33 39 (39) ahvsup 43 (41) ahvss 66 (57) avsup 13 (18) dvsup 16 (19) dvss 21 (24) resetq 62 (56) avss 35 (35) vref1 26 (27) vref2 5 v 5 v 8 v avss 5v 5v capl_m (40) 40 capl_a (38) 38 agndc (42) 45 xtal_in (62) 71 xtal_out (63) 72 dpl 4519g d_ctr_i/o_0 (5) 78 d_ctr_i/o_1 (4) 77 aud_cl_out (1) 74 testen (61) 70 + 100 w 100 w 100 w 100 w 22 m f 22 m f 22 m f 22 m f + + + 1 nf 1 nf 1 nf dacm_sub (31) 30 dacm_r (28) 27 dacm_l (29) 28 1 m f 1 m f 1 m f right + 3.3 m f 100 nf 8v(5v) 18.432 mhz + + 10 m f 10 m f 60 (55) mono_in 56 (52) sc1_in_l 57 (53) sc1_in_r 55 (51) asg 53 (49) sc2_in_l 54 (50) sc2_in_r 52 (48) asg 50 (46) sc3_in_l 51 (47) sc3_in_r 49 (45) asg 47 (43) sc4_in_l 48 (44) sc4_in_r 80 (7) standbyq 79 (6) adr_sel 3 (10) i2c_da 2 (9) i2c_cl 5 (12) i2s_ws 4 (11) i2s_cl 7 (14) i2s_da_in1 17 (20) i2s_da_in2 6 (13) i2s_da_out 220 pf ahvss ahvss ahvss 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf dvss dvss ahvss c s. section 4.6.2. resetq (from controller, see section 4.6.3.3.) note: decoupling capacitors from - dvsup to dvss, - avsup to avss, and - ahvsup to ahvss are recommended as closely as possible to supply pins (see application note on page 42). 1.5 nf 470 pf 10 m f 1.5 nf 470 pf 10 m f 1.5 nf 470 pf 10 m f (5 v) ahvss ahvss ahvss daca_r (25) 24 1 nf 1 nf daca_l (26) 25 1 m f 1 m f note: pin numbers refer to the pqfp80 package, numbers in brackets refer to the psdip64 package. subwoofer left center surround
preliminary data sheet dpl 4519g micronas 63
all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. dpl 4519g preliminary data sheet 64 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-512-1pd 6. data sheet history 1. preliminary data sheet: "dpl 4519g sound proces- sor for digital and analog surround systems", oct. 31, 2000, 6251-512-1pd. first release of the preliminary data sheet.

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